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csim.js |
options.xul |
options.js |
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consts.js |
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b2a.c
var regRI = (regRE = (regPC = (regTB = (regTA = (regHI = 26) + 1) + 1) + 1) + 1) + 1;
var instr = {
oc_000001 : {
name: 'pdi', type: 'i',
code: 'setReg(subPdIn(im_v))'
},
oc_000010 : {
name: 'pdo', type: 'i',
code: 'subPdOut(rg_alp_v, im_v)'
},
oc_000011 : {
name: 'hi ', type: 'i',
code: 'setReg((rg_alp_v & 4194303) + im_v * Math.pow(2, 22))'
},
oc_000100 : {
name: 'set', type: 'i',
code: 'setReg(im_v)'
},
oc_000101 : {
name: 'add', type: 'i',
code: 'setReg(rg_alp_v + im_v)'
},
oc_000110 : {
name: 'sub', type: 'i',
code: 'setReg(rg_alp_v - im_v)'
},
oc_000111 : {
name: 'mul', type: 'i',
code: 'setReg(rg_alp_v * im_v)'
},
oc_001000 : {
name: 'div', type: 'i',
code: 'setReg(Math.floor(rg_alp_v / im_v))'
},
oc_001001 : {
name: 'mod', type: 'i',
code: 'setReg(rg_alp_v % im_v)'
},
oc_001010 : {
name: 'pca', type: 'i',
code: 'setReg(cheapReg[regPC] + im_v)'
},
oc_001011 : {
name: 'pcs', type: 'i',
code: 'setReg(cheapReg[regPC] - im_v)'
},
oc_001100 : {
name: 'and', type: 'i',
code: 'setReg(opr_and(rg_alp_v, im_v))'
},
oc_001101 : {
name: 'or ', type: 'i',
code: 'setReg(opr_or(rg_alp_v, im_v))'
},
oc_001110 : {
name: 'xor', type: 'i',
code: 'setReg(opr_xor(rg_alp_v, im_v))'
},
oc_001111 : {
name: 'shl', type: 'i',
code: 'setReg(opr_shl(rg_alp_v, im_v))'
},
oc_010000 : {
name: 'shr', type: 'i',
code: 'setReg(opr_shr(rg_alp_v, im_v))'
},
oc_010001 : {
name: 'rtl', type: 'i',
code: 'setReg(opr_or(opr_shl(rg_alp_v, im_v), opr_shr(rg_alp_v, cheapReg.length - im_v)))'
},
oc_010010 : {
name: 'rtr', type: 'i',
code: 'setReg(opr_or(opr_shl(rg_alp_v, cheapReg.length - im_v), opr_shr(rg_alp_v, im_v)))'
},
oc_010011 : {
name: 'fbs', type: 'i',
code: 'setReg(rg_alp_v + (opr_shr(rg_alp_v, im_v) % 2 ? 0 : Math.pow(2, im_v)))'
},
oc_010100 : {
name: 'cbs', type: 'i',
code: 'setReg(opr_shr(rg_alp_v, im_v) % 2)'
},
oc_010101 : {
name: 'cst', type: 'i',
code: 'setReg(rg_alp_v < im_v ? 1 : 0)'
},
oc_010110 : {
name: 'cgt', type: 'i',
code: 'setReg(rg_alp_v > im_v ? 1 : 0)'
},
oc_010111 : {
name: 'ce ', type: 'i',
code: 'setReg(rg_alp_v == im_v ? 1 : 0)'
},
oc_011000 : {
name: 'jmp', type: 'j',
code: 'setReg(im_v, regPC)'
},
oc_011001 : {
name: 'jmr', type: 'j',
code: 'setReg(cheapReg[regPC], regRE); setReg(im_v, regPC)'
},
oc_011010 : {
name: 'bez', type: 'i',
code: 'if (! rg_alp_v) setReg(im_v, regPC)'
},
oc_011011 : {
name: 'bgz', type: 'i',
code: 'if (rg_alp_v) setReg(im_v, regPC)'
},
oc_011100 : {
name: 'isp', type: 'i',
code: 'cheapIrq[rg_alp_v].isrPos = im_v'
},
oc_011101 : {
name: 'lda', type: 'j',
code: 'for (var i = im_v; i < im_v + regNum; setReg(cheapMem[i], i++));'
},
oc_011110 : {
name: 'sva', type: 'j',
code: 'for (var i = im_v; i < im_v + regNum; setMem(cheapReg[i], i++));'
},
oc_011111 : {
name: 'dta', type: 'j',
code: ''
},
sc_000001: {
name: 'pdi', type: 'r',
code: 'setReg(subPdIn(rg_bet_v))'
},
sc_000010: {
name: 'pdo', type: 'r',
code: 'subPdOut(rg_alp_v, rg_bet_v)'
},
sc_000011: {
name: 'hi ', type: 'r',
code: 'setReg((rg_alp_v & 4194303) + rg_bet_v * Math.pow(2, 22))'
},
sc_000100: {
name: 'set', type: 'r',
code: 'setReg(rg_bet_v)'
},
sc_000101: {
name: 'add', type: 'r',
code: 'setReg(rg_alp_v + rg_bet_v)'
},
sc_000110: {
name: 'sub', type: 'r',
code: 'setReg(rg_alp_v - rg_bet_v)'
},
sc_000111: {
name: 'mul', type: 'r',
code: 'setReg(rg_alp_v * rg_bet_v)'
},
sc_001000: {
name: 'div', type: 'r',
code: 'setReg(Math.floor(rg_alp_v / rg_bet_v))'
},
sc_001001: {
name: 'mod', type: 'r',
code: 'setReg(rg_alp_v % rg_bet_v)'
},
sc_001010: {
name: 'pca', type: 'r',
code: 'setReg(cheapReg[regPC] + rg_bet_v)'
},
sc_001011: {
name: 'pcs', type: 'r',
code: 'setReg(cheapReg[regPC] - rg_bet_v)'
},
sc_001100: {
name: 'and', type: 'r',
code: 'setReg(opr_and(rg_alp_v, rg_bet_v))'
},
sc_001101: {
name: 'or ', type: 'r',
code: 'setReg(opr_or(rg_alp_v, rg_bet_v))'
},
sc_001110: {
name: 'xor', type: 'r',
code: 'setReg(opr_xor(rg_alp_v, rg_bet_v))'
},
sc_001111: {
name: 'shl', type: 'r',
code: 'setReg(opr_shl(rg_alp_v, rg_bet_v))'
},
sc_010000: {
name: 'shr', type: 'r',
code: 'setReg(opr_shr(rg_alp_v, rg_bet_v))'
},
sc_010001: {
name: 'rtl', type: 'r',
code: 'setReg(opr_or(opr_shl(rg_alp_v, rg_bet_v), opr_shr(rg_alp_v, cheapReg.length - rg_bet_v)))'
},
sc_010010: {
name: 'rtr', type: 'r',
code: 'setReg(opr_or(opr_shl(rg_alp_v, cheapReg.length - rg_bet_v), opr_shr(rg_alp_v, rg_bet_v)))'
},
sc_010011: {
name: 'fbs', type: 'r',
code: 'setReg(rg_alp_v + (opr_shr(rg_alp_v, rg_bet_v) % 2 ? 0 : Math.pow(2, rg_bet_v)))'
},
sc_010100: {
name: 'cbs', type: 'r',
code: 'setReg(opr_shr(rg_alp_v, rg_bet_v) % 2)'
},
sc_010101: {
name: 'cst', type: 'r',
code: 'setReg(rg_alp_v < rg_bet_v ? 1 : 0)'
},
sc_010110: {
name: 'cgt', type: 'r',
code: 'setReg(rg_alp_v > rg_bet_v ? 1 : 0)'
},
sc_010111: {
name: 'ce ', type: 'r',
code: 'setReg(rg_alp_v == rg_bet_v ? 1 : 0)'
},
sc_011000: {
name: 'jmp', type: 's',
code: 'setReg(rg_alp_v, regPC);'
},
sc_011001: {
name: 'jmr', type: 's',
code: 'setReg(cheapReg[regPC], regRE); setReg(rg_bet_v, regPC)'
},
sc_011010: {
name: 'bez', type: 'r',
code: 'if (! rg_alp_v) setReg(rg_bet_v, regPC)'
},
sc_011011: {
name: 'bgz', type: 'r',
code: 'if (rg_alp_v) setReg(rg_bet_v, regPC)'
},
sc_011100: {
name: 'isp', type: 'r',
code: 'cheapIrq[rg_alp_v].isrPos = rg_bet_v'
},
sc_011101: {
name: 'lda', type: 's',
code: 'for (var i = rg_bet_v; i < rg_bet_v + regNum; setReg(cheapMem[i], i++));'
},
sc_011110: {
name: 'sva', type: 's',
code: 'for (var i = rg_bet_v; i < rg_bet_v + regNum; setMem(cheapReg[i], i++));'
},
sc_110000: {
name: 'lw ', type: 'r',
code: 'setReg(cheapMem[rg_bet_v])'
},
sc_110001: {
name: 'sw ', type: 'r',
code: 'setMem(rg_alp_v, rg_bet_v)'
},
sc_110010: {
name: 'xch', type: 'r',
code: 'setReg(rg_bet_v, rg_alp_n); setReg(rg_alp_v, rg_bet_n)'
},
sc_110011: {
name: 'isd', type: 'v',
code: 'chrUpdIrqState(servedInt.pop(), "s", "i"); cheapReg[regPC] = cheapReg[regRI]'
},
sc_110100: {
name: 'ird', type: 'v',
code: 'irqEnabledCnt = -2'
},
sc_110101: {
name: 'ire', type: 'v',
code: 'irqEnabledCnt = -1'
}
};