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00014 #ifndef PSPINTRMAN_H
00015 #define PSPINTRMAN_H
00016
00017 #include <pspkerneltypes.h>
00018
00025
00026 #ifdef __cplusplus
00027 extern "C" {
00028 #endif
00029
00030 extern const char* PspInterruptNames[67];
00031
00032 enum PspInterrupts
00033 {
00034 PSP_GPIO_INT = 4,
00035 PSP_ATA_INT = 5,
00036 PSP_UMD_INT = 6,
00037 PSP_MSCM0_INT = 7,
00038 PSP_WLAN_INT = 8,
00039 PSP_AUDIO_INT = 10,
00040 PSP_I2C_INT = 12,
00041 PSP_SIRCS_INT = 14,
00042 PSP_SYSTIMER0_INT = 15,
00043 PSP_SYSTIMER1_INT = 16,
00044 PSP_SYSTIMER2_INT = 17,
00045 PSP_SYSTIMER3_INT = 18,
00046 PSP_THREAD0_INT = 19,
00047 PSP_NAND_INT = 20,
00048 PSP_DMACPLUS_INT = 21,
00049 PSP_DMA0_INT = 22,
00050 PSP_DMA1_INT = 23,
00051 PSP_MEMLMD_INT = 24,
00052 PSP_GE_INT = 25,
00053 PSP_VBLANK_INT = 30,
00054 PSP_MECODEC_INT = 31,
00055 PSP_HPREMOTE_INT = 36,
00056 PSP_MSCM1_INT = 60,
00057 PSP_MSCM2_INT = 61,
00058 PSP_THREAD1_INT = 65,
00059 PSP_INTERRUPT_INT = 66
00060 };
00061
00062 enum PspSubInterrupts
00063 {
00064 PSP_GPIO_SUBINT = PSP_GPIO_INT,
00065 PSP_ATA_SUBINT = PSP_ATA_INT,
00066 PSP_UMD_SUBINT = PSP_UMD_INT,
00067 PSP_DMACPLUS_SUBINT = PSP_DMACPLUS_INT,
00068 PSP_GE_SUBINT = PSP_GE_INT,
00069 PSP_DISPLAY_SUBINT = PSP_VBLANK_INT
00070 };
00071
00077 unsigned int sceKernelCpuSuspendIntr(void);
00078
00084 void sceKernelCpuResumeIntr(unsigned int flags);
00085
00091 void sceKernelCpuResumeIntrWithSync(unsigned int flags);
00092
00100 int sceKernelIsCpuIntrSuspended(unsigned int flags);
00101
00107 int sceKernelIsCpuIntrEnable(void);
00108
00119 int sceKernelRegisterSubIntrHandler(int intno, int no, void *handler, void *arg);
00120
00129 int sceKernelReleaseSubIntrHandler(int intno, int no);
00130
00139 int sceKernelEnableSubIntr(int intno, int no);
00140
00149 int sceKernelDisableSubIntr(int intno, int no);
00150
00151 typedef struct tag_IntrHandlerOptionParam{
00152 int size;
00153 u32 entry;
00154 u32 common;
00155 u32 gp;
00156 u16 intr_code;
00157 u16 sub_count;
00158 u16 intr_level;
00159 u16 enabled;
00160 u32 calls;
00161 u32 field_1C;
00162 u32 total_clock_lo;
00163 u32 total_clock_hi;
00164 u32 min_clock_lo;
00165 u32 min_clock_hi;
00166 u32 max_clock_lo;
00167 u32 max_clock_hi;
00168 } PspIntrHandlerOptionParam;
00169
00170 int QueryIntrHandlerInfo(SceUID intr_code, SceUID sub_intr_code, PspIntrHandlerOptionParam *data);
00171
00172 #ifdef __cplusplus
00173 }
00174 #endif
00175
00178 #endif